View APDS-9190_7161959.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

APDS-9190 digital proximity sensor data sheet description the APDS-9190 provides ir led and a complete digital proximity detection system in a single 8 pin package. the proximity function ofers plug and play detection to 100 mm (without front glass) thus eliminating the need for factory calibration of the end equipment or sub-assembly. the proximity detection feature operates well from bright sunlight to dark rooms. the wide dynamic range also allows for operation in short distance detection behind dark glass such as a cell phone. the proximity function is targeted specifcally towards near feld proximity applications. in cell phones, the proximity detection can detect when the user positions the phone close to their ear. the device is fast enough to provide proximity information at a high repetition rate needed when answering a phone call. this provides both improved green power saving capability and the added security to lock the computer when the user is not present. the addition of the micro-optics lenses within the module, provide highly efcient transmission and reception of infrared energy which lowers overall power dissipation. features ? ir led and proximity detector in an optical module ? proximity detection C fully calibrated to 100 mm detection C integrated ir led and synchronous led driver C eliminates factory calibration of prox C covers a 2000: 1 dynamic range ? programmable wait timer C wait state power C 70 a typical C programmable from 2.72 ms to > 6 sec ? i 2 c interface compatible C up to 400 khz (i 2 c fast-mode) C dedicated interrupt pin ? sleep mode power - 2.5 a typical ? small package l3.94 x w2.36 x h1.35 mm applications ? cell phone touch-screen disable ? notebook/monitor security ? automatic speakerphone enable ? automatic menu pop-up ? digital camera eye sensor 6 - gnd 7 - scl 8 - vdd 1 - sda 5 - led a 3 - ldr 2 - sint 4 - led k ordering information part number packaging quantity APDS-9190 tape & reel 2500 per reel
2 functional block diagram upper threshold lower threshold interrupt i 2 c interface control logic prox detect adc data int scl sda vdd gnd ldr led k led a prox ir led ch0 ch1 led regulated constant current sink detailed description the APDS-9190 light-to-digital device provides on-chip ch0 and ch1 diodes, integrating amplifers, adcs, accu - mulators, clocks, bufers, comparators, a state machine and an i 2 c interface. each device combines one ch0 photodiode (visible plus infrared) and one infrared- responding (ir) photodiode. two integrating adcs simul - taneously convert the amplifed photodiode currents to a digital value providing up to 16-bits of resolution. upon completion of the conversion cycle, the conversion result is transferred to the ch0 and ir data registers. this digital output can be read by a microprocessor. communication to the device is accomplished through a fast (up to 400 khz), two-wire i 2 c serial bus for easy con - nection to a microcontroller or embedded controller. the digital output of the APDS-9190 device is inherently more immune to noise when compared to an analog interface. the APDS-9190 provides a separate pin for level-style in - terrupts. when interrupts are enabled and a pre-set value is exceeded, the interrupt pin is asserted and remains asserted until cleared by the controlling frmware. the interrupt feature simplifes and improves system efciency by eliminating the need to poll a sensor for a proximity value. an interrupt is generated when the value of proximity conversion exceeds either an upper or lower threshold. additionally, a programmable interrupt per - sistence feature allows the user to determine how many consecutive exceeded thresholds are necessary to trigger an interrupt. interrupt thresholds and persistence settings are confgured independently for proximity. proximity detection is fully provided with an 850 nm ir led. an internal led driver (ldr) pin, is jumper connected to the led cathode (led k) to provide a factory calibrated proximity of 100 +/- 20 mm. this is accomplished with a proprietary current calibration technique that accounts for all variances in silicon, optics, package and most impor - tantly ir led output power. this will eliminate or greatly reduce the need for factory calibration that is required for most discrete proximity sensor solutions. while the APDS-9190 is factory calibrated at a given pulse count, the number of proximity led pulses can be programmed from 1 to 255 pulses, which will allow greater proximity distances to be achieved. each pulse has a 16 s period.
3 i/o pins confguration pin name type description 1 sda i/o i 2 c serial data i/o terminal C serial data i/o for i 2 c. 2 int o interrupt C open drain. 3 ldr i led driver for proximity emitter C up to 100 ma, open drain. 4 ledk o led cathode, connect to ldr pin in most systems to use internal led driver circuit 5 leda i led anode, connect to vbatt on pcb 6 gnd power supply ground. all voltages are referenced to gnd. 7 scl i i 2 c serial clock input terminal C clock signal for i 2 c serial data. 8 vdd power supply voltage. absolute maximum ratings over operating free-air temperature range (unless otherwise noted) ? parameter symbol min max units conditions power supply voltage v dd 3.8 v 1 digital voltage range -0.5 3.8 v digital output current i o -1 20 ma storage temperature range tstg -40 85 c ? stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may afect device reliability. note: 1. all voltages are with respect to gnd. recommended operating conditions parameter symbol min typ max units operating ambient temperature t a -30 85 c supply voltage v dd 2.5 3.0 3.6 v interface bus power supply voltage v bus 1.8 v supply voltage accuracy, v dd total error including transients -3 +3 % led supply voltage v bat t 2.5 4.5 v operating characteristics, v dd = 3 v, t a = 25 c (unless otherwise noted) parameter symbol min typ max units test conditions supply current [1] i dd 175 250 a active 70 wait mode 2.5 4.0 sleep mode int sda output low voltage v ol 0 0.4 v 3 ma sink current 0 0.6 6 ma sink current leakage current, sda, scl, int pins i leak -5 5 a leakage current, ldr pin i leak 10 a scl, sda input high voltage v ih 1.25 v scl, sda input low voltage v il 0.54 v oscillator frequency fosc 705 750 795 khz pon = 1 note: 1. the power consumption is raised by the programmed amount of proximity led drive during the 8 us the led pulse is on. the nominal and maximum values are shown under proximity characteristics. there the i dd supply current is i dd active + proximity led drive programmed value.
4 proximity characteristics, v dd = 3 v, t a = 25 c, pgain=1, pen = 1 (unless otherwise noted) parameter symbol min typ max units test conditions supply current C ldr pulse on i dd 3 ma adc conversion time step size 2.72 ms ptime = 0xf adc number of integration steps 1 steps ptime = 0xf full scale adc counts per steps 1023 counts ptime = 0xf proximity ir led pulse count 0 255 pulses proximity pulse period 16.3 s proximity pulse C led on time 7.2 s proximity led drive 100 ma pdrive=0 i sink sink current @ 600 mv, ldr pin 50 pdrive =1 25 pdrive =2 12.5 pdrive =3 proximity adc count value, no object 100 led driving 8 pulses, pdrive = 0, open view (no glass) and no refective object above the module. proximity adc count value 416 520 624 counts refecting object C 73 x 83 mm kodak 90% grey card, 100 mm distance, led driving 8 pulses, pdrive = 0, open view (no glass) above the module. ir led characteristics, v dd = 3 v, t a = 25 c parameter symbol min typ max units test conditions forward voltage v f 1.4 1.5 v i f = 20 ma reverse voltage v r 5 v i r = 10 a radiant power p o 4.5 mw i f = 20 ma peak wavelength p 850 nm i f = 20 ma spectrum width, half power 40 nm i f = 20 ma optical rise time t r 20 ns i f = 100 ma optical fall time t f 20 ns i f = 100 ma wait characteristics, v dd = 3 v, t a = 25 c, wen = 1 (unless otherwise noted) parameter min typ max units test conditions wait step size 2.72 ms wtime = 0xf wait number of step 1 256 steps
5 characteristics of the sda and scl bus lines, v dd = 3 v, t a = 25 c (unless otherwise noted) ? parameter symbol standard-mode fast-mode unit min. max. min. max. scl clock frequency f scl 0 100 0 400 khz hold time (repeated) start condition. after this period, the frst clock pulse is generated t hd;sta 4.0 C 0.6 C s low period of the scl clock t low 4.7 C 1.3 C s high period of the scl clock t high 4.0 C 0.6 C s set-up time for a repeated start condition t su;sta 4.7 C 0.6 C s data hold time: t hd;dat 0 C 0 C ns data set-up time t su;dat 250 C 100 C ns rise time of both sda and scl signals t r 20 1000 20 300 ns fall time of both sda and scl signals t f 20 300 20 300 ns set-up time for stop condition t su;sto 4.0 C 0.6 C s bus free time between a stop and start condition t buf 4.7 C 1.3 C s capacitive load for each bus line cb C 400 C 400 pf noise margin at the low level for each connected device (including hysteresis) v nl 0.1 v bus C 0.1 v bus C v noise margin at the high level for each connected device (including hysteresis) v nh 0.2 v bus C 0.2 v bus C v ? specifed by design and characterization; not production tested. figure 1. i 2 c bus timing diagram s sr t su;sto t su;sta t hd;sta t high t low t su;dat t hd;dat t f sda scl p s t buf t r t f t r t sp t hd;sta msc610 sda scl stop start scl ack t (lowmext) t (lowmext) t (lowsext) scl ack t (lowmext)
6 figure 2. spectral responsivity figure 3. normalized i dd vs. v dd figure 4. normalized i dd vs. temperature figure 5a. normalized pd responsivity vs. angular displacement figure 5b. normalized led angular emitting profle 0.8 1.0 1.2 300 400 500 600 700 800 900 1000 1100 wavelength (nm) normalized responsitivity ch 0 ch 1 0.0 0.2 0.4 0.6 0.8 0.9 1.0 1.1 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 v dd (v) normalized i dd @ 3 v 25 c 0.8 0.9 1.0 1.1 1.2 -60 -40 -20 0 20 40 60 80 100 temperature (c) normalized i dd @ 3 v 0.8 0.9 1.0 1.1 -100 -80 -60 -40 -20 0 20 40 60 80 100 angle (degree) normalized responsitivity 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 normalised radiant intensity angle (degree)
7 principles of operation system state machine the APDS-9190 provides control of proximity detection and power management functionality through an internal state machine. after a power-on-reset, the device is in the sleep mode. as soon as the pon bit is set, the device will move to the start state. it will then continue through the prox and wait states. if these states are enabled, the device will execute each function. if the pon bit is set to a 0, the state machine will continue until all conversions are completed and then go into a low power sleep mode. figure 6. simplifed state diagram note: in this document, the nomenclature uses the bit feld name in italics followed by the register number and bit number to allow the user to easily identify the register and bit that controls the function. for example, the power on (pon) is in register 0, bit 0. this is represented as pon (r0:b0). proximity detection proximity sensing uses an internal ir led light source to emit light which is then viewed by the integrated light detector to measure the amount of refected light when an object is in the light path. the amount of light detected from a refected surface can then be used to determine an objects proximity to the sensor. the APDS-9190 is factory calibrated to meet the requirement of proximity sensing of 100 +/- 20 mm, thus eliminating the need for factory calibration of the end equipment. when the APDS-9190 is placed behind a typical glass surface, the proximity detection achieved is around 25 to 40 mm, thus providing an ideal touch-screen disable. the APDS-9190 has controls for the number of ir pulses (ppcount), the integration time (ptime), the led drive current (pdrive) and the photodiode confguration (pdiode). the photodiode confguration can be set to no diode (test mode), infrared diode (recommended), ch0 diode or a combination of both diodes. at the end of the integration cycle, the results are latched into the proximity data (pdata) register. the led drive current is controlled by a regulated current sink on the ldr pin. this feature eliminates the need to use a current limiting resistor to control led current. the led drive current can be confgured for 12.5 ma, 25 ma, 50 ma, or 100ma. for higher led drive requirements, an external p type transistor can be used to control the led current. the number of led pulses can be programmed to a value of 1 to 255 pulses as needed. increasing the number of led pulses at a given current will increase the sensor sen - sitivity. sensitivity grows by the square root of the number of pulses. each pulse has a 16 s period. the proximity integration time (ptime) is the period of time that the internal adc converts the analog signal to a digital count. it is recommend that this be set to a minimum of ptime = 0xff or 2.72 ms. figure 7. proximity ir led waveform sleep start wait prox pon = 1 (r0:b0) pon = 0 (r0:b0) led o irled pulses subtract background add ir+ background led on 16 s
8 optical design considerations the APDS-9190 simplifes the optical system design by eliminating the need for light pipes and improves system optical efciency by providing apertures and package shielding which will reduce crosstalk when placed in the fnal system. by reducing the ir led to glass surface crosstalk, proximity performance is greatly improved and enables a wide range of cell phone applications utilizing the APDS-9190. the module package design has been optimized for minimum package foot print and short distance proximity of 100 mm typical. the spacing between the glass surface and package top surface is critical to controlling the crosstalk. if the package to top surface spacing gap, window thickness and transmittance are met, there should be no need to add additional com - ponents (such as a barrier) between the led and photo - diode. thus with some simple mechanical design imple - mentations, the APDS-9190 will perform will in the end equipment system. figure 8. proximity detection air gap, g plastic/glass window APDS-9190 windows thickness, t the APDS-9190 is available in a low profle package that contains optics which provides optical gain on both the led and the sensor side of the package. the device has a package z height of 1.35 mm and will support air gap of < = 0.5 mm between the glass and the package. the assumption of the optical system level design is that glass surface above the module is < = to 1.0 mm. by integrating the micro-optics in the package, the ir energy emitted can be reduced thus conserving the precious battery life in the application. the system designer has the ability to optimize their designs for slim form factor z height as well as improve the proximity sensing, save battery power and disable the touch screen in a cellular phone. APDS-9190 module optimized design parameters ? window thickness, t 1.0 mm ? air gap, g 0.5 mm ? assuming window ir transmittance 90% figure 9b. ps output vs. distance, at various pulse number (led drive current). no glass in front of the module, 90% kodak grey card figure 9a. ps output vs. distance, at various pulse number (led drive current). no glass in front of the module, 18% kodak grey card 0 200 400 600 800 1000 1200 ps count distance (cm) 0 200 400 600 800 1000 1200 ps count distance (cm) 4p (100 ma) 6p (100 ma) 8p (100 ma) 16p (100 ma) 8p (50 ma) 2 4 6 8 10 12 14 16 0 0 4 8 6 10 12 14 16 18 20 2 8p (100 ma) 4p (100 ma) 16p (100 ma) 8p (50 ma) 6p (100 ma)
9 interrupts the interrupt feature of the APDS-9190 simplifes and improves system efciency by eliminating the need to poll the sensor for a light intensity or proximity value. the interrupt mode is determined by the pien or aien feld in the enable register. the APDS-9190 implements four 16-bit-wide interrupt threshold registers that allow the user to defne thresholds above and below a desired light level. an interrupt can be generated when the proximity data (pdata) exceeds the upper threshold value (pihtx) or falls below the lower threshold (piltx). to further control when an interrupt occurs, the APDS-9190 provides an interrupt persistence feature. this feature allows the user to specify a number of conver - sion cycles for which an event exceeding the proximity interrupt threshold must persist (ppers) before actually generating an interrupt. refer to the register descriptions for details on the length of the persistence. figure 10. programmable interrupt p ihth (r0 x ob), p ihtl (r0 x oa) p ilth (r09), p ihtl (r08) a pers (r0 x oc, b3:0) prox integration prox adc prox data upper limit prox persistence lower limit ch1 state diagram the following shows a more detailed fow for the state machine. the device starts in the sleep mode. the pon bit is written to enable the device. if the pen bit is set, the state machine will step through the proximity states of proximity accumulate and then proximity adc con - version. as soon as the conversion is complete, the state machine will move to the following state. if the wen bit is set, the state machine will then cycle through the wait state. if the wlong bit is set, the wait cycles are extended by 12x over normal operation. pon = 1 pon = 0 wen = 1 pen = 1 sleep start prox accum prox check prox adc up to 255 led pulses pulse frequency: 60 khz time: 16.3 s ? 4.2 ms maximum ? 4.2 ms up to 255 steps step: 2.72 ms time: 2.72 ms ? 696 ms recommended ? 2.72 ms 1024 counts wlong = 0 counts up to 256 steps step: 2.72 ms time: 2.72 ms ? 696 ms maximum ? 2.72 ms wlong = 1 counts up to 256 steps step: 32.64 ms time: 32.64 ms ? 8.35 ms maximum ? 32.64 ms wait wait check figure 11. extended state diagram
10 power management power consumption can be controlled through the use of the wait state timing since the wait state consumes only 70 a of power. the following shows an example of using the power management feature to achieve an average power consumption of 140 a of current with 4 C 100 ma pulses of proximity detection. example: 50 ms cycle time state duration current(ma) prox accum (led on) 0.064 (0.032) 100 prox adc 2.72 0.175 wait 47 0.070 avg = ((0.032 x 100) + (2.72 x 0.175) + (47 x 0.070)) 50 = 140 a figure 12. power consumption calculations 4 irled pulses prox accum prox adc wait 64 s (32 s led on time) 2.72 ms 47 ms
11 basic software operation the following pseudo-code shows how to do basic initialization of the APDS-9190. uint8 ptime,wtime,ppcount; wtime = 0xf; // 2.7ms C minimum wait time ptime = 0xf; // 2.7ms C minimum prox integration time ppcount = 1; // minimum prox pulse count writeregdata(0, 0); //disable and powerdown writeregdata (2, ptime); writeregdata (3, wtime); writeregdata (0xe, ppcount); uint8 pdrive, pdiode, pgain, again; pdrive = 0; //100ma of led power pdiode = 0x20; // ch1 diode pgain = 0; //1x prox gain writeregdata (0xf, pdrive | pdiode | pgain | again); uint8 wen, pen, pon; wen = 8; // enable wait pen = 4; // enable prox pon = 1; // enable power on writeregdata (0, wen | pen | pon); // writeregdata(0,0x0f ); wait(12); //wait for 12 ms int prox_data; prox_data = read_word(0x18); writeregdata(uint8 reg, uint8 data) { m_i2cbus.writei2c(0x39, 0x80 | reg, 1, &data); } uint16 read_word(uint8 reg); { uint8 barr[2]; m_i2cbus.readi2c(0x39, 0xa0 | reg, 2, ref barr); return (uint16)(barr[0] + 256 * barr[1]);
12 i 2 c protocol interface and control of the APDS-9190 is accomplished through an i 2 c serial compatible interface (standard or fast mode) to a set of registers that provide access to device control functions and output data. the device supports a single slave address of 0x39 hex using 7 bit addressing protocol. (contact factory for other addressing options.) the i 2 c standard provides for three types of bus trans - action: read, write and a combined protocol. during a write operation, the frst byte written is a command byte followed by data. in a combined protocol, the frst byte written is the command byte followed by reading a series start and stop conditions of bytes. if a read command is issued, the register address from the previous command will be used for data access. likewise, if the msb of the command is not set, the device will write a series of bytes at the address stored in the last valid command with a register address. the command byte contains either control information or a 5 bit register address. the control commands can also be used to clear interrupts. for a complete description of i 2 c protocols, please review the i 2 c specifcation at: http://www.nxp. com data transfer on i 2 c-bus a complete data transfer s 1 ? 7 8 9 1 ? 7 8 9 1 ? 7 8 9 p stop condition start condition data data address ack ack ack r/w sda scl sda scl 1 7 2 8 acknowledgement signal from slave msb start or repeated start condition byte complete, interrupt within slave s or sr ack clock line held low while interrupts are serviced ack 9 sr or p 1 2 3 to 8 9 acknowledgement signal from receiver stop or repeated start condition sr p 1 2 3 to 8 9 ack msb msb scl sda s p start condition stop condition
13 a acknowledge (0) n not acknowledged (1) p stop condition r read (1) s start condition sr repeated start condition w write (0) continuation of protocol master-to-slave slave-to-master i 2 c write protocol 1 7 1 1 8 1 8 1 1 s slave address w a command code a data a p i 2 c write protocol (clear interrupt) 1 7 1 1 8 1 1 s slave address w a command code a p i 2 c write word protocol 1 7 1 1 8 1 8 1 8 1 1 s slave address w a command code a data low a data high a p i 2 c read protocol C combined format 1 7 1 1 8 1 1 7 1 1 8 1 1 s slave address w a command code a sr slave address r a data high n p i 2 c read word protocol 1 7 1 1 8 1 1 7 1 1 8 1 s slave address w a command code a sr slave address r a data low a 8 1 1 data high n p
14 register set the APDS-9190 is controlled and monitored by data registers and a command register accessed through the serial interface. these registers provide for a variety of control functions and can be read to determine results of the adc conversions. address resister name r/w register function reset value C command w specifes register address 0x00 0x00 enable r/w enable of states and interrupts 0x00 0x02 ptime r/w proximity adc time 0xff 0x03 wtime r/w wait time 0xff 0x08 piltl r/w proximity interrupt low threshold low byte 0x00 0x09 pilth r/w proximity interrupt low threshold hi byte 0x00 0x0a pihtl r/w proximity interrupt hi threshold low byte 0x00 0x0b pihth r/w proximity interrupt hi threshold hi byte 0x00 0x0c pers r/w interrupt persistence flters 0x00 0x0d config r/w confguration 0x00 0x0e ppcount r/w proximity pulse count 0x00 0x0f control r/w gain control register 0x00 0x11 rev r revision number rev 0x13 status r device status 0x00 0x18 pdatal r proximity adc low data register 0x00 0x19 pdatah r proximity adc high data register 0x00 the mechanics of accessing a specifc register depends on the specifc protocol used. see the section on i 2 c protocols on the previous pages. in general, the command register is written frst to specify the specifc control/status register for following read/write operations.
15 command register the command registers specifes the address of the target register for future write and read operations. 7 6 5 4 3 2 1 0 command cmd type add -- field bits description command 7 select command register. must write as 1 when addressing command register. type 6:5 selects type of transaction to follow in subsequent data transfers: field value integration time 00 repeated byte protocol transaction 01 auto-increment protocol transaction 10 reserved C do not use 11 special function C see description below byte protocol will repeatedly read the same register with each data access. block protocol will provide auto-increment function to read successive bytes. add 4:0 address register/special function register. depending on the transaction type, see above, this feld either specifes a special function command or selects the specifc control-status-register for following write or read transactions: field value read value 00000 normal C no action 00101 proximity interrupt clear 00111 proximity interrupt clear other reserved C do not write proximity interrupt clear. clears any pending proximity interrupt. this special function is self clearing. enable register (0x00) the enable register is used primarily to power the APDS-9190 device up and down as shown in table 4. 7 6 5 4 3 2 1 0 address enable reserved reserved pien reserved wen pen reserved pon 0x00 field bits description reserved 7:6 reserved. write as 0. pien 5 proximity interrupt enable. when asserted, permits proximity interrupts to be generated. reserved 4 reserved. write as 0. wen 3 wait enable. this bit activates the wait feature. writing a 1 activates the wait timer. writing a 0 disables the wait timer. pen 2 proximity enable. this bit activates the proximity function. writing a 1 enables proximity. writing a 0 disables proximity. reserved 1 reserved. write as 0. pon 0 power on. this bit activates the internal oscillator to permit the timers and adc channels to operate. writing a 1 activates the oscillator. writing a 0 disables the oscillator. notes: 1. a 2.7-ms delay is automatically inserted prior to entering the adc cycle, independent of the wen bit. 2. pon must be asserted before the adc channels will operate correctly. 3. during writes and reads over the i 2 c interface, this bit is overridden and the oscillator is enabled, independent of the state of pon. 4. a minimum interval of 2.7 ms must pass after pon is asserted before proximity can be initiated. this required time is enforced by the hardware in cases where the frmware does not provide it.
16 proximity time control register (0x02) the proximity timing register controls the integration time of the proximity adc in 2.72 ms increments. it is recom - mended that this register be programmed to a value of 0xf (1 cycle, 1023 bits). field bits description ptime 7:0 value cycles time max count 0xf 1 2.72 ms 1023 wait time register (0x03) wait time is set 2.72 ms increments unless the wlong bit is asserted in which case the wait times are 12x longer. wtime is programmed as a 2s complement number. field bits description wtime 7:0 register value wait time time (w long = 0) time (w long = 1) 0xf 1 2.72 ms 0.032 sec 0xb6 74 201.29 ms 2.37 sec 0x00 256 696.32 ms 8.19 sec notes: 1. the write byte protocol cannot be used when wtime is greater than 127. 2. the proximity wait time register should be confgured before pen is asserted. proximity interrupt threshold register (0x08 C 0x0b) the proximity interrupt threshold registers provide the values to be used as the high and low trigger points for the com - parison function for interrupt generation. if the value generated by proximity channel crosses below the lower threshold specifed, or above the higher threshold, an interrupt is signaled to the host processor. register address bits description piltl 0x08 7:0 proximity adc channel low threshold lower byte pilth 0x09 7:0 proximity adc channel low threshold upper byte pihtl 0x0a 7:0 proximity adc channel high threshold lower byte pihth 0x0b 7:0 proximity adc channel high threshold upper byte
17 persistence register (0x0c) the persistence register controls the fltering interrupt capabilities of the device. confgurable fltering is provided to allow interrupts to be generated after each adc integration cycle or if the adc integration has produced a result that is outside of the values specifed by threshold register for some specifed amount of time. 7 6 5 4 3 2 1 0 pers ppers reserved 0x0c field bits description ppers 7:4 proximity interrupt persistence. controls rate of proximity interrupt to the host processor. field value meaning interrupt persistence function 0000 every every proximity cycle generates an interrupt 0001 1 1 consecutive proximity values out of range ... ... ... 1111 15 15 consecutive proximity values out of range confguration register (0x0d) the confguration register sets the wait long time. 7 6 5 4 3 2 1 0 config reserved wlong reserved 0x0d field bits description reserved 7:2 reserved. write as 0. wlong 1 wait long. when asserted, the wait cycles are increased by a factor 12x from that programmed in the wtime register. reserved 0 reserved. write as 0. proximity pulse count register (0x0e) the proximity pulse count register sets the number of proximity pulses that will be transmitted. ppcount defnes the number of pulses to be transmitted at a 62.5 khz rate. 7 6 5 4 3 2 1 0 ppcount ppcount 0x0e field bits description ppcount 7:0 proximity pulse count. specifes the number of proximity pulses to be generated.
18 control register (0x0f) the gain register provides eight bits of miscellaneous control to the analog block. these bits typically control functions such as gain settings and/or diode selection. 7 6 5 4 3 2 1 0 control pdrive pdiode pgain reserved 0x0f field bits description pdrive 7:6 led drive strength. field value led strength 00 100 ma 01 50 ma 10 25 ma 11 12.5 ma pdiode 5:4 proximity diode select. field value diode selection 00 reserved 01 reserved 10 proximity uses the ch1 diode 11 reserved pgain 3:2 proximity gain control. field value proximity gain value 00 1x gain 01 reserved 10 reserved 11 reserved reserved 1:0 reserved. write as 0. rev id register (0x11) the rev id register provides the silicon revision number. the rev id is a read-only register whose value never changes. 7 6 5 4 3 2 1 0 rev rev id 0x11 field bits description rev id 7:0 revision number identifcation 0x01
19 status register (0x13) the status register provides the internal status of the device. this register is read only. 7 6 5 4 3 2 1 0 status reserved reserved pint reserved reserved reserved pvalid reserved 0x13 field bits description reserved 7:6 reserved. pint 5 proximity interrupt. indicates that the device is asserting a proximity interrupt. reserved 4:2 reserved. pvalid 1 proximity interrupt. indicates that the device is asserting a proximity interrupt. reserved 0 reserved. proximity data register (0x18 ? 0x19) proximity data is stored as a 16-bit value. to ensure the data is read correctly, a two byte read i 2 c transaction should be utilized with a read word protocol bit set in the command register. with this operation, when the lower byte register is read, the upper eight bits are stored into a shadow register, which is read by a subsequent read to the upper byte. the upper register will read the correct value even if additional adc integration cycles end between the reading of the lower and upper registers. register address bits description pdata 0x18 7:0 proximity data low byte pdatah 0x19 7:0 proximity data high byte
20 application information: hardware the application hardware circuit for implementing proximity system solution is quite simple with the APDS-9190 and is shown in following fgure. the 1 f decoupling capacitors should be low esr to reduce noise. it further recommended to maximize system performance the use of power and ground planes is recommended in the pcb. if mounted on a fexible circuit, the power and ground traces back to the pcb should be sufciently wide enough to have a low resistance, such as < 1 ohm. figure 13. circuit implementation for proximity solution using the APDS-9190 gnd APDS-9190 mcu vdd v bus vdd 1 f 1 f 10 k? 10 k? 10 k? vbatt gpio scl sda int scl sda ldr led k led a
21 pcb pad layout suggested pcb pad layout guidelines for the dual flat no-lead surface mount package are shown below. notes: all linear dimensions are in mm. 0.60 0.60 0.72 (x8) 0.25 (x6) 0.80 package outline dimensions 1 2 3 4 4 3 2 1 ? 1 0.05 ? 0.90 0.05 1.18 0.05 0.58 0.05 2.40 0.05 134 2.10 0.1 2.36 0.2 1.35 0.20 3.73 0.1 3.94 0.2 pinout 1 - sda 2 - int 3 - ldr 4 - ledk 5 - leda 6 - gnd 7 - scl 8 - vdd 0.80 0.60 0.05 0.05 0.25 (x6) 0.72 (x8) 5 6 7 8 5 6 7 8
22 tape dimensions all dimensions unit: mm k0 a0 b0 12 +0.30 -0.10 4 0.10 ? 1.50 0.10 1.75 0.10 2 0.05 8 0.10 5.50 0.05 ? 1 0.05 unit orientation a a 4.30 0.10 0.29 0.02 1.70 0.10 6 max 2.70 0.10 8 max reel dimensions
23 moisture proof packaging all APDS-9190 options are shipped in moisture proof package. once opened, moisture absorption begins. this part is compliant to jedec msl 3. units in a sealed mositure-proof package package is opened (unsealed) environment less than 30 deg c, and less than 60% rh ? package is opened less than 168 hours ? perform recommended baking conditions no baking is necessary no yes no yes recommended storage conditions: storage temperature 10 c to 30 c relative humidity below 60% rh time from unsealing to soldering: after removal from the bag, the parts should be soldered within 168 hours if stored at the recommended storage conditions. if times longer than 168 hours are needed, the parts must be stored in a dry box baking conditions: package temp. time in reels 60 c 48 hours in bulk 100 c 4 hours if the parts are not stored in dry conditions, they must be baked before refow to prevent damage to the parts. baking should only be done once.
for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies in the united states and other countries. data subject to change. copyright ? 2005-2013 avago technologies. all rights reserved. av02-3182en - june 4, 2013 recommended refow profle 50 100 300 150 200 250 t-time (seconds) 25 80 120 150 180 200 230 255 0 t - temperature (c) r1 r2 r3 r4 r5 217 max 260 c p1 heat up p2 solder paste dry p3 solder reflow p4 cool down 60 sec to 120 sec above 217 c the refow profle is a straight-line representation of a nominal temperature profle for a convective refow solder process. the temperature profle is divided into four process zones, each with diferent t/ time tem - perature change rates or duration. the t/ time rates or duration are detailed in the above table. the temperatures are measured at the component to printed circuit board connections. in process zone p1 , the pc board and component pins are heated to a temperature of 150 c to activate the fux in the solder paste. the temperature ramp up rate, r1, is limited to 3 c per second to allow for even heating of both the pc board and component pins. process zone p2 should be of sufcient time duration (100 to 180 seconds) to dry the solder paste. the temperature is raised to a level just below the liquidus point of the solder. process zone p3 is the solder refow zone. in zone p3, the temperature is quickly raised above the liquidus point of solder to 260 c (500 c ) for optimum results. the dwell time above the liquidus point of solder should be between 60 and 120 seconds. this is to assure proper coalescing of the solder paste into liquid solder and the formation of good solder connections. beyond the recommended dwell time the intermetallic growth within the solder con - nections becomes excessive, resulting in the formation of weak and unreliable connections. the temperature is then rapidly reduced to a point below the solidus temperature of the solder to allow the solder within the connections to freeze solid. process zone p4 is the cool down after solder freeze. the cool down rate, r5, from the liquidus point of the solder to 25 c (77 f) should not exceed 6 c per second maximum. this limitation is necessary to allow the pc board and component pins to change dimensions evenly, putting minimal stresses on the component. it is recommended to perform refow soldering no more than twice. process zone symbol t maximum t/ time or duration heat up p1, r1 25 c to 150 c 3c/s solder paste dry p2, r2 150 c to 200 c 100 s to 180 s solder refow p3, r3 p3, r4 200 c to 260 c 260 c to 200 c 3c/s -6c/s cool down p4, r5 200 c to 25 c -6c/s time maintained above liquidus point, 217 c > 217 c 60 s to 120 s peak temperature 260 c C time within 5 c of actual peak temperature > 255 c 20 s to 40 s time 25 c to peak temperature 25 c to 260 c 8 mins

▲Up To Search▲

Price & Availability of APDS-9190

	To Download APDS-9190 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .